The present invention relates to the fabrication of semiconductor integrated circuits, and more specifically to an apparatus and method of making strained semiconductor complementary metal oxide semiconductor (CMOS) transistors having lattice-mismatched source and drain regions.
Both theoretical and empirical studies have demonstrated that carrier mobility with a transistor is greatly increased when a strain is applied to the transistor's conduction channel. In p-type field effect transistors, the application of a compressive longitudinal strain to the conduction channel is known to increase the drive currents of the PFET. However, if that same strain is applied to the conduction channel of an NFET, its performance decreases.
It has been proposed to apply a tensile longitudinal strain to the conduction channel of an NFET and apply a compressive longitudinal strain to the conduction channel of a PFET. Such proposals have focused on masked processes involving the masking of a PFET or NFET portion of the chip and altering the materials used in shallow trench isolation regions to apply the strain. The proposals have also included masked processes centered on modulating intrinsic stresses present in spacer features.
Silicon germanium is a desirable lattice-mismatched semiconductor for use in forming strained silicon transistor channels. A strain is created when a first semiconductor is grown onto a single-crystal of a second semiconductor when the two semiconductors are lattice-mismatched to each other. Silicon and silicon germanium are lattice-mismatched to each other such that the growth of one of them onto the other produces a strain which can be either tensile or compressive.
Silicon germanium grows epitaxially on silicon having a crystal structure aligned with the silicon crystal structure. However, because silicon germanium normally has a larger crystal structure than silicon, the epitaxially grown silicon germanium becomes internally compressed.
In other proposals using strained silicon, silicon germanium forms a single-crystal layer of an entire substrate. In such case, the silicon germanium layer is known as a relaxed layer, because the strain is released by forming dislocations within the silicon germanium layer. When a single-crystal silicon layer is grown epitaxially on a relaxed SiGe crystal region, a tensile strain is produced in the epitaxially grown silicon crystal. This results in improved electron mobility, which is capable of improving the performance of an NFET.
However, such technique requires the SiGe to be relaxed, which requires that the SiGe layer be very thick, i.e. 0.5 to 1.0 μm. Improvements in the mobility of holes is difficult to obtain because to do so, the SiGe layer requires a large percentage of germanium, which can result in excessive dislocations in the SiGe crystal, causing yield problems. Further, processing costs can be prohibitive.
Other techniques such as graded Ge concentration and chemical mechanical polishing methods are used to improve the quality of the films. However, those techniques are plagued by high cost and high defect density.
Accordingly, it would be desirable to create a strain in the channel region of a PFET without the use of a thick SiGe crystal region. It would be desirable create a desired strain in a channel region of a device using a relatively thin epitaxially grown SiGe.
It would further be desirable to create a compressive strain to increase hole mobility in the channel region of a PFET by growing an epitaxial layer of SiGe in the source and drain regions of the PFET.
It would further be desirable to provide a process for applying a desired strain in the channel region of a PFET without creating the same strain in the channel region of the NFET.